1. Technical Field
The present disclosure relates to retiming regions of an electronic circuit design to improve the efficiency of parallel simulation of the electronic circuit design.
2. Description of the Related Arts
Logic simulation of multi-core computing systems continues to become more complex and more important in the overall design process. Parallel logic simulation techniques claim to increase the performance of simulation task by taking advantage of concurrent read-write access of VLSI systems. Simulation of logic designs at gate, register transfer, and behavioral level of physical abstraction can employ different techniques, such as event driven and oblivious
Parallel logic simulation techniques, like parallel event driven simulation, employ multiple time-ordered queues and partitions, and assign sections of a design into a time-ordered queue running on a processor. Generally, event driven simulation maintains a time ordered queue. Components with value changes are inserted into the queue which limits the computation to parts of the design that have to be updated. To operate properly, the time ordered queues need to be synchronized. Parallel event driven simulation, however, does not scale well beyond four or eight processors in practice. Synchronization cost between hundreds of processors can be very high and at each time step and each level of the logic under test. Moreover, the simulation work assignment may not be distributed evenly among the processors performing the simulation.
Other parallel logic simulation techniques, like oblivious simulation, evaluate all components of the logic design under test. That is, a component of the logic design is evaluated whether or not it has a value change or not. And in turn, the computation of a component is simpler compared to parallel event driven simulation because a value change of a component is not checked, and queue insertion is not performed. In further contrast to parallel event driven simulation, parallel oblivious simulation does not suffer work starvation in processors. Synchronization can be simpler since a single synchronization per level of the model is sufficient. Parallel oblivious simulation, however, may be less efficient for certain simulation task because parallel oblivious simulation performs redundant computation. For example, in cases where the number of value changes per design clock is low, parallel oblivious simulation is slower than serial event driven simulation.